Technical Field
The present invention relates to an organic light emitting display device and a method of manufacturing the same, and more particularly, to an organic light emitting display device which may implement high resolution and a method of manufacturing the same.
Discussion of the Related Art
Display devices, which display various pieces of information on a screen, are a core technology in the age of information and communication and have been developed to satisfy thinness, light-weight, portability and high-performance trends. Therefore, as a flat panel display which can reduce weight and volume to make up for drawbacks of a cathode ray tube (CRT), an organic light emitting display device, which controls the amount of light emitted from an organic light emitting layer and thus displays an image, is now spotlighted. Such an organic light emitting display device is a self-luminous display and has advantages, such as low power consumption, high response speed, high luminous efficacy, high brightness and wide viewing angle.
Such an organic light emitting display device displays an image through a plurality of sub-pixels arranged in a matrix. Each of the sub-pixels includes a light emitting element and a pixel circuit including a plurality of transistors to independently drive the light emitting element.
Here, the light emitting element is formed on the transistors of the pixel circuit separately from the transistors through a separate mask process. Therefore, an emission area EA, in which the light emitting element is disposed, vertically overlaps a transistor area TA, in which the transistors are disposed, as exemplarily shown in FIG. 1. However, a storage capacitor included in the pixel circuit is formed to be coplanar with the transistors through the same mask process as the transistors. Therefore, a capacitor area CA, in which the storage capacitor is disposed, does not overlap the transistor area TA and is spaced from the transistor area TA in the horizontal direction. Further, signal lines connected to the transistors, for example, data lines DL, a high voltage (VDD) supply line VL1 and a low voltage (VSS) supply line VL2 are arranged to be spaced apart from each other in the horizontal direction in consideration of influence of a parasitic capacitor. Since the signal lines DL, VL1 and VL2, the transistor area TA and the capacitor area CA should be arranged to be spaced apart from one another in the horizontal direction on a substrate, it may be difficult to implement high resolution due to an insufficient process margin and yield may be lowered.